The present invention relates to a semiconductor device having a vertical transistor, and a method of manufacturing the same.
As a semiconductor device, known is a semiconductor device having vertical transistors. A vertical transistor is used in, for example, an element for controlling a large electric current. As described in, for example, Patent Literature 1 (listed up below), a vertical transistor has a structure having an n-layer which is to be a drain, a p-layer which is formed on the n-layer and is to be a channel layer, and an n-layer which is formed on the front surface of the p-layer and is to be a source. In a device described in Patent Literature 1, a planar MOS transistor is formed in the same substrate in which the vertical transistor is formed. This planar MOS transistor is configured as a control circuit of a power device section made of the vertical transistor.
Patent Literature 2 (see below) states that when a planar MOS transistor is subjected to hydrogen annealing treatment, the MOS transistor recovers from damages which the MOS transistor receives in the manufacturing method thereof.